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Staff or above, Package Design Engineer <外商 Fabless house>

新竹 全職 在家工作或混合工作模式 查看職務說明
We are seeking an experienced Package Design Engineer to lead the development of advanced package solutions for high-performance products. This role involves close collaboration with design, manufacturing, and customer teams to ensure package designs meet electrical, thermal, mechanical, reliability, and production requirements.
  • Work on advanced packaging technologies from QFN to WLCSP and flip-chip solution
  • Collaborate with global engineering teams and product development.

關於我們的客戶

Our client is a leading global fabless company focused on developing innovative semiconductor solutions for consumer and electronics applications. With a strong engineering culture and commitment to technical excellence, the organization invests heavily in advanced product development, employee growth, and cross-functional collaboration across international teams.

職務說明

  • Lead package design activities for advanced semiconductor products, ensuring performance, reliability, and manufacturability targets are achieved.
  • Define electrical, mechanical, and thermal package requirements in collaboration with IC design and layout teams.
  • Utilize package design and simulation tools to develop physical layouts, validate designs, and support manufacturing readiness.
  • Establish and maintain package design rules for technologies such as WLCSP, wire bond, flip-chip, and other advanced packaging solutions.
  • Perform design-for-manufacturing (DFM) reviews and implement improvements to enhance assembly yield and reduce production risks.
  • Drive continuous improvement and automation initiatives throughout the package development process.
  • Develop and evaluate test vehicles to validate package performance and signal integrity considerations.
  • Partner closely with customers, manufacturing partners, and internal stakeholders to resolve design challenges and optimize package implementation.



理想的應徵者

  • Bachelor's degree or above in Mechanical Engineering, Electrical Engineering, Materials Science, Chemical Engineering, or a related discipline.
  • 5+ years of experience in semiconductor packaging or a related technical field.
  • Hands-on experience with package layout tools, particularly Cadence SiP Layout and AutoCAD.
  • Strong understanding of package materials, substrate design, assembly processes, and packaging technologies.
  • Ability to interpret electrical simulation results and apply them to package optimization.
  • Excellent communication and stakeholder management skills with the ability to present technical concepts to both engineering and leadership teams.
  • Self-motivated, detail-oriented, and capable of driving projects independently.
  • Experience with PCB, die layout, simulation, or advanced design tools is highly desirable.



福利待遇

  • Competitive compensation package and performance-based rewards.
  • Exposure to cutting-edge semiconductor packaging technologies and global product development programs.
  • Opportunities for technical leadership, career advancement, and continuous professional development.
  • Collaborative, inclusive, and innovation-driven work environment.
  • Flexible working arrangement with hybrid work opportunities and access to advanced engineering resources and training programs.



聯絡
Eddie Chien
職務編號
JN-072026-7071893
手機號
+886 2 8729 8260

職務概要

職務類別
工程與製造
子類別
電子
產業
半導體
地區
新竹
合約類型
全職
招募顧問名稱
Eddie Chien
招募顧問電話
+886 2 8729 8260
職務編號
JN-072026-7071893
辦公模式
在家工作或混合工作模式

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