Staff Analog Layout Engineer

台灣 全職 查看職務說明
This role focuses on end-to-end analog IC layout, from block-level design to full-chip integration. You will ensure design quality through physical verification and optimise performance using deep layout expertise. The position also involves project coordination and mentoring responsibilities.
  • Work on high-precision analog ICs with full-chip ownership
  • Lead projects and mentor juniors in a globally collaborative engineering team

關於我們的客戶

Our client is a globally recognised semiconductor company specialising in high-performance analog and mixed-signal solutions. With a strong presence across international markets, the organisation is known for its engineering excellence, innovation, and collaborative culture.

職務說明

  • Execute analog IC layout from block level to top-level integration, including floorplanning and package considerations.
  • Perform physical verification tasks such as DRC, LVS, antenna checks, and sign-off processes.
  • Apply advanced layout techniques to address matching, parasitics, LDE, ESD protection, and latch-up concerns.
  • Optimise layout for performance factors such as noise isolation, power integrity, and manufacturability.
  • Coordinate project timelines, allocate resources, and support team execution.
  • Provide guidance and technical leadership to junior layout engineers.



理想的應徵者

  • Degree in Electrical Engineering or related field, with 5+ years of experience in analog/mixed-signal layout.
  • Strong expertise in full-chip or block-level layout, floorplanning, and physical design optimisation.
  • Solid understanding of analog circuits such as ADCs, DACs, LDOs, bandgap references, and amplifiers.
  • Knowledge of semiconductor processes, device matching, EM/IR analysis, shielding, and reliability considerations.
  • Familiar with layout verification flows and DFM requirements.
  • Effective communicator in English, with the ability to collaborate across regions.
  • Self-driven, detail-oriented, and capable of working in team-based environments.



福利待遇

  • Competitive compensation package aligned with market standards.
  • Opportunity to work on cutting-edge analog IC products and advanced process technologies.
  • Exposure to global projects and cross-functional collaboration.
  • Clear career progression with leadership and technical growth opportunities.
  • Supportive working environment that encourages innovation and continuous learning.



聯絡
Eddie Chien
職務編號
JN-062026-7034436
手機號
+886 2 8729 8260

職務概要

職務類別
工程與製造
子類別
製圖/CAD
產業
半導體
地區
台灣
合約類型
全職
招募顧問名稱
Eddie Chien
招募顧問電話
+886 2 8729 8260
職務編號
JN-062026-7034436

Michael Page的多元化與包容性

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