Save Job Back to Search Job Description Summary Similar JobsWork on post-quantum security chips for global AI and edge marketsJoin a fast-growing semiconductor company expanding into Silicon ValleyAbout Our Client Our client is an innovative semiconductor company focused on developing post-quantum security chips and advanced AI-ready hardware solutions.Headquartered in Taiwan, the company is actively expanding globally with a presence in Silicon Valley and participation in the prestigious Silicon Catalyst accelerator. It is also engaged in international defence-related projects and building strong partnerships across global supply chains.The company's technology plays a critical role in securing AI systems, protecting models and sensitive data from emerging cybersecurity threats. Initial applications focus on autonomous systems, with expansion into AI surveillance and edge computing devices.This is an opportunity to join a globally ambitious company at an early stage, working on highly differentiated and future-critical semiconductor technologies.Job DescriptionLead full-chip and block-level physical implementation from netlist to GDSII, including floorplanning, placement, CTS, and routingDrive advanced node design optimization for N7/N5/N3 technologies, addressing challenges such as multi-patterning, LDE, and FinFET effectsExecute sign-off closure, including static timing analysis (STA), IR drop, electromigration (EM), and physical verification (DRC/LVS)Implement low-power design techniques, including multi-voltage domains and power gating using UPF/CPF methodologiesDevelop and maintain automation scripts (Tcl/Python) to improve design productivity and PPA (Power, Performance, Area)Collaborate with cross-functional teams to ensure design quality and successful tape-out deliveryOptimize large-scale, high-complexity designs with focus on signal integrity, timing convergence, and power efficiencyThe Successful ApplicantMaster's degree in Electrical Engineering, Computer Science, or related fields10+ years of experience in physical design / APR, with at least one successful tape-out on advanced nodes (N7/N5/N3)Strong expertise in EDA tools such as Cadence Innovus or Synopsys ICC2 / Fusion CompilerProficient in sign-off tools including PrimeTime / Tempus, Voltus / RedHawk, and CalibreDeep understanding of hierarchical design, variation-aware STA (POCV), and signal integrityStrong experience working on large-scale chip designs (>10M gates)Preferred SkillsExperience in advanced packaging technologies (2.5D / 3D IC such as CoWoS, InFO)Familiarity with high-speed interface requirements (PCIe Gen5/6, DDR5)Knowledge of FinFET processes, color-aware routing, EM/IR optimization, and noise analysisAdvanced scripting capabilities in Tcl, Python, or PerlPersonal AttributesStrong problem-solving skills and attention to detailAbility to work in fast-paced, high-performance engineering environmentsProactive, accountable, and results-driven mindsetEffective communicator and collaborative team playerWhat's on OfferOpportunity to work on next-generation post-quantum and AI security semiconductor technologiesExposure to advanced node design (N7/N5/N3) and leading-edge chip developmentGlobal project exposure with Silicon Valley and international ecosystem collaborationFast-growing company with strong expansion plans and innovation focusHigh-impact role contributing directly to successful tape-outs and product innovationDynamic and collaborative engineering environment with strong technical leadershipContactJill LaiQuote job refJN-062026-7043163Phone number+886287298222Job summaryJob functionEngineering & ManufacturingSpecialisationEngineering Design, R&D and NPIWhat is your area of specialisation?SemiconductorsLocationTaipei CityContract TypePermanentConsultant nameJill LaiConsultant phone+886287298222Job ReferenceJN-062026-7043163
