(Processor/CPU) Senior RTL Design Lead

新竹 全職 查看職務說明
This role focuses on leading the design and delivery of processor RTL, from architecture definition through silicon validation. You will guide a team while ensuring high-quality implementation that meets performance, power, and area targets.
  • Lead end-to-end CPU RTL design and influence next-gen processor architecture
  • High-impact leadership role with ownership across design, verification, delivery

關於我們的客戶

Our client is an innovative semiconductor company specialising in advanced processor and SoC development. With a strong engineering culture, they focus on cutting-edge technologies including CPU architecture, AI acceleration, and high-performance computing solutions.

職務說明

  • Drive end-to-end RTL development for processor subsystems, from specification to tape-out
  • Define microarchitecture, including pipeline design, cache hierarchy, and system interconnects
  • Ensure robust designs through proper clocking, reset strategies, timing closure, and low-power techniques
  • Collaborate with verification, physical design, DFT, and software teams to ensure successful silicon delivery
  • Oversee validation processes including simulation, formal checks, and post-silicon debugging
  • Lead design reviews, enforce development standards, and manage technical risks
  • Improve efficiency through scripting, automation, and CI/regression flow enhancements



理想的應徵者

  • Extensive experience in RTL design using SystemVerilog/Verilog with multiple successful ASIC tape-outs
  • Solid expertise in CPU or processor microarchitecture (pipeline, cache, coherency, branch prediction)
  • Familiarity with industry-standard EDA tools for simulation, synthesis, and sign-off
  • Strong understanding of verification methodologies, STA, and design quality checks (CDC, lint, formal)
  • Proven leadership experience managing engineering teams and cross-functional collaboration
  • Proficiency in scripting (Python, Tcl, Shell) and automation workflows
  • Strong analytical thinking, debugging capability, and ability to make decisions under pressure



福利待遇

  • Competitive compensation package aligned with senior technical leadership roles
  • Opportunity to work on advanced processor technologies and complex SoC designs
  • Clear career progression into higher technical or architectural leadership positions
  • Collaborative and innovation-driven working environment with global exposure
聯絡
Eddie Chien
職務編號
JN-062026-7050426
手機號
+886 2 8729 8260

職務概要

職務類別
工程與製造
子類別
積體電路設計/ 半導體
產業
半導體
地區
新竹
合約類型
全職
招募顧問名稱
Eddie Chien
招募顧問電話
+886 2 8729 8260
職務編號
JN-062026-7050426

Michael Page的多元化與包容性

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