儲存工作 返回搜尋 職務說明 概要 類似職務Own end-to-end digital verification from spec to system-level validationWork on mixed-signal ICs with strong exposure to UVM, AMS, and modelling關於我們的客戶Our client is a global semiconductor company specialising in advanced Power IC solutions. They provide a highly collaborative engineering environment with strong emphasis on innovation, verification excellence, and product quality.職務說明Lead and manage the digital verification environment across projectsDefine verification methodologies, flows, and best practicesTranslate specifications into detailed verification plans and frameworksDevelop SystemVerilog models, assertions, and testbenchesSupport mixed-signal verification through AMS environments and modellingContribute to digital sub-block design where required理想的應徵者Bachelor's with 5+ years or Master's with 3+ years of relevant experienceStrong background in digital verification, including multiple tape-out cyclesProficient in SystemVerilog, UVM, and verification methodologiesExperience with Cadence tools (Virtuoso, AMS) and analog-mixed signal environmentsCapable of analog schematic exploration and real-number modelling (preferred)Skilled in debugging simulation issues and identifying root causesFamiliar with scripting languages such as Python, TCL, or cshSelf-driven and able to collaborate effectively in remote, cross-functional teams福利待遇Competitive salary with performance-based incentivesOpportunity to work on complex mixed-signal IC developmentExposure to advanced verification methodologies and toolsCollaborative, international engineering environment with career growth opportunities聯絡Minna Wu職務編號JN-062026-7047284手機號+886287298206職務概要職務類別工程與製造子類別測試/應用/調試產業半導體地區新竹合約類型全職招募顧問名稱Minna Wu招募顧問電話+886287298206職務編號JN-062026-7047284
