Analog IC Designer (Serdes/PLL/Clocking/LDO/Power/ADC)

This hiring covers multiple positions, matched to the candidate's background and strengths:1) Analog Design Engineer (General Analog)

• Design core analog circuits such as bandgap references, bias circuits, LDOs, voltage/current references, and sensors.
• Develop power management, monitoring, and analog support blocks including ADC/DAC-related circuitry.
• Own block-level delivery from specification, schematic design, simulation, layout collaboration, to post-silicon validation.

2) Analog Design Engineer - High-Speed I/O

• Design high-speed TX/RX, analog front-end, SerDes-related blocks, drivers/receivers, and impedance calibration circuits.
• Implement equalization techniques such as FFE, CTLE, and DFE, and support clocking interactions (e.g., CDR).
• Perform signal integrity analysis, eye margin evaluation, and develop IBIS/IBIS-AMI models; support silicon bring-up.

3) Analog Design Engineer - PLL / Clocking

• Design and debug PLL/DLL architectures (integer or fractional-N), including VCO/DCO and frequency synthesis.
• Develop low-jitter clock generation, distribution, calibration, and clock management circuits.
• Conduct phase noise and jitter analysis, behavioral modeling, and post-silicon correlation.

Across all roles, engineers will collaborate closely with layout, verification, and system teams, ensuring robust design sign-off and successful IP integration.